diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c
index 42207b2..af07a11 100644
--- a/arch/arc/lib/cache.c
+++ b/arch/arc/lib/cache.c
@@ -231,6 +231,34 @@
 
 	while (read_aux_reg(ARC_AUX_SLC_CTRL) & SLC_CTRL_BUSY);
 }
+
+static void arc_ioc_setup(void)
+{
+	/* IOC Aperture start is equal to DDR start */
+	unsigned int ap_base = CONFIG_SYS_SDRAM_BASE;
+	/* IOC Aperture size is equal to DDR size */
+	long ap_size = CONFIG_SYS_SDRAM_SIZE;
+
+	flush_n_invalidate_dcache_all();
+
+	if (!is_power_of_2(ap_size) || ap_size < 4096)
+		panic("IOC Aperture size must be power of 2 and bigger 4Kib");
+
+	/*
+	 * IOC Aperture size decoded as 2 ^ (SIZE + 2) KB,
+	 * so setting 0x11 implies 512M, 0x12 implies 1G...
+	 */
+	write_aux_reg(ARC_AUX_IO_COH_AP0_SIZE,
+		      order_base_2(ap_size / 1024) - 2);
+
+	/* IOC Aperture start must be aligned to the size of the aperture */
+	if (ap_base % ap_size != 0)
+		panic("IOC Aperture start must be aligned to the size of the aperture");
+
+	write_aux_reg(ARC_AUX_IO_COH_AP0_BASE, ap_base >> 12);
+	write_aux_reg(ARC_AUX_IO_COH_PARTIAL, 1);
+	write_aux_reg(ARC_AUX_IO_COH_ENABLE, 1);
+}
 #endif /* CONFIG_ISA_ARCV2 */
 
 #ifdef CONFIG_ISA_ARCV2
@@ -324,32 +352,8 @@
 #ifdef CONFIG_ISA_ARCV2
 	read_decode_cache_bcr_arcv2();
 
-	if (ioc_exists) {
-		/* IOC Aperture start is equal to DDR start */
-		unsigned int ap_base = CONFIG_SYS_SDRAM_BASE;
-		/* IOC Aperture size is equal to DDR size */
-		long ap_size = CONFIG_SYS_SDRAM_SIZE;
-
-		flush_n_invalidate_dcache_all();
-
-		if (!is_power_of_2(ap_size) || ap_size < 4096)
-			panic("IOC Aperture size must be power of 2 and bigger 4Kib");
-
-		/*
-		 * IOC Aperture size decoded as 2 ^ (SIZE + 2) KB,
-		 * so setting 0x11 implies 512M, 0x12 implies 1G...
-		 */
-		write_aux_reg(ARC_AUX_IO_COH_AP0_SIZE,
-			      order_base_2(ap_size / 1024) - 2);
-
-		/* IOC Aperture start must be aligned to the size of the aperture */
-		if (ap_base % ap_size != 0)
-			panic("IOC Aperture start must be aligned to the size of the aperture");
-
-		write_aux_reg(ARC_AUX_IO_COH_AP0_BASE, ap_base >> 12);
-		write_aux_reg(ARC_AUX_IO_COH_PARTIAL, 1);
-		write_aux_reg(ARC_AUX_IO_COH_ENABLE, 1);
-	}
+	if (ioc_exists)
+		arc_ioc_setup();
 
 	read_decode_mmu_bcr();